A register and a cache are different.

You have to ask a cache, “Do you currently have the value of memory location X?” This is called a probe and it takes time. The answer can come back “no” (miss) or “yes” (hit). Modern CPUs require something on the order of 3 cycles to access their first level cache.

There are no register file “hits” or “misses”. The code asks for register #10, you go get it. That’s it. It’s always there. Register files can be read/written multiple times in a single clock cycle. A register-to-register move, for example, takes exactly 1 cycle.

It’s not an accident that today’s CPUs have synchronous L1 caches. It’s not because hardware designers didn’t ever think, “Hey, what if we made the cache run twice as fast?”

We make everything run as fast as it possibly can. This is measured in pico-seconds, which is an absolute measurement. Clock cycles are relative. At 3Ghz a clock is 330 picoseconds. So on my hardware, an ADD takes 330 picoseconds. An L1 cache hit takes 990.

You can slow your execution units down if you want. You can perform the ADD in 2790 picoseconds, and then claim your cache runs “twice as fast.” I won’t be impressed until you can do a cache probe in less than 990 pico seconds.

–Mark

PS: The “to-memory” operations above are due to the keyword “volatile” from the C language. http://en.wikipedia.org/wiki/Volatile_variable

Yes, it is more transistors than a normal register array. But, then, the Intel philosophy is to just throw more transistors at things anyway. For all we know, Intel and AMD processors are already doing precisely this, which is likely why your compilers elected to perform “to-memory” operations instead of “to-register” operations.