A clean design is about more than just pulling speed paths out of legacy modes. I’m talking about potentially needing to access memory 15 separate times in order to execute a single load/store instruction I’m talking about wasting a cycle to find out where you are in a register file. (Yes, flat mode is available now for the FPU, but this is the sort of thing that never even comes up in a clean design.)

One of the useful things at working at an evil company for a while was that I got to learn about a totally different architecture. Not that it was still clean, but it opened up the possibilities.

When I originally wrote this, I was thinking more along the lines of “if we spoke some RISC ISA instead of x86″, although, admittedly, this is not what Crosby said. It makes sense that removing the “legacy modes” would improve things other than the front end, for example (as you note) something like the load store unit.

I guess I’m willing to believe your “5-10% fewer non-cache” transistors, but I still have a somewhat hard time accepting the clock advantages. Are there really speed paths through this legacy stuff?

Going back to the LSU as an example, K8 still supports the segmented addressing scheme, but you pay another cycle whenever you use it. Seems less like “overhead” and more like “pay as you go”.

Away, thanks again for the comment. Good to see another AMDer somewhere besides comp.arch :)

So 55% of transistors are made up on the spot.